The present invention relates to a logic circuit with a logic gate section which is constructed of IGFET's (insulated gate field effect transistors) and is able to change a bias voltage properly.
A logic circuit as an amplifier which is comprised of CMOS (complementary metal oxide silicon) transistors and has a structure as shown in FIG. 1 is disclosed in U.S. Pat. No. 3,914,702. In the logic circuit, bias voltages at nodes 2 and 3 are controlled by a control signal applied to a control terminal 1. In FIG. 1, reference numerals 5 and 6 designate P-channel type IGFET's (referred to merely as transistors) and numerals 7 and 8 N-channel type IGFET's. The transistors 6 and 7, making up an inverter IN, are connected at the gates to an input terminal 9. The output of the inverter IN is connected to an output terminal 10. In the logic circuit, even a slight change of the voltage at the control terminal 1 causes a gm ratio (conductance ratio) of the transistors 5 and 8 to change. Therefore, voltages at the nodes 2 and 3 change greatly. Therefore, with the voltage change at the control terminal 1, a potential at an operating point (a center in an input amplitude) of the inverter IN changes. Further, since the control signal is supplied only from the control signal terminal 1, an amplitude of the output from the inverter IN is limited.